This invention relates to high speed CMOS integrated circuits, and specifically to a method of SiGe relaxation and shallow trench isolation which is suitable for commercial CMOS production.
SiGe relaxation after shallow trench isolation (STI) has been proposed to reduce defect density and junction leakage current.
In enhanced mobility MOSFET device applications, thick, relaxed Si1xe2x88x92xGex buffer layers have been used as virtual substrates for thin strained silicon layers to increase carrier mobility for NMOS devices, as reported by Welser et al., Strain dependence of the performance enhancement in strained-Si n-MOSFETs, IEDM Conference Proceedings, p. 373 (1994); Rim et al., Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs, IEDM Conference Proceedings, p. 517 (1995); and Nayak et al., High-mobility Strained-Si PMOSFETs, IEEE Transactions on Electron Devices, Vol. 43, 1709 (1996).
Hxc3x6ck et al., High hole mobility in Si0.17Ge0.83 channel metal-oxide-semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition, Applied Physics letters, 76, 3920, 2000, report fabrication of a p-MOSFET on a stained relieved SiGe buffer.
H. Trinkaus et al, Strain relaxation mechanism for hydrogen-implanted Si1xe2x88x92xGex/Si(100) heterostructures, Appl. Phys. Lett., 76, 3552, 2000, have reported the advantages of using hydrogen implantation to increase the degree of SiGe relaxation and to reduce the density of threading dislocation. However, a relaxation of a SiGe layer of between 2000 xc3x85 and 2500 xc3x85 was reported. A SiGe layer of such thickness is not sufficient for commercial device application. Likewise, the other reports of CMOS devices on strained relieved SiGe layers do not provide techniques which are commercially viable.
A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer at a dose of between about 1xc3x971016cmxe2x88x922 to 4xc3x971016cmxe2x88x922, and at an energy level properly adjusted to have a projected depth of between about 2 nm to 100 nm deeper than the SiGe:silicon interface. For a layer of SiGe having a thickness of about 300 nm, the hydrogen ion energy level is between about 40 keV to 80 keV. The method of the invention further includes forming a trench by shallow trench isolation, which extends into the substrate; annealing the structure at a temperature of between about 700xc2x0 C. to 900xc2x0 C. for between about five minutes to sixty minutes to relax the strained SiGe layer; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
It is an object of this invention to provide a process integration flow on a CMOS Si1xe2x88x92xGex device for high speed integration circuit.
Another object of the invention is to fabricate a CMOS Si1xe2x88x92xGex device using STI which does not have a notch at the SiGe active edge.